microcontroller

LKS32MC453RCT8

Symbol
P0_1/MCPWM1_BKIN2/UART0_RXD/SPI0_CSN/TIM4_CH1/CAN_TX/EXTI1/5VT1P0_2/CMP5_OUT/MCPWM1_BKIN3/UART0_TXD/CAN_RX/CMP5_IP0/WAKE0/EXTI2/5VT2P0_3/HALL1_IN2/SPI0_DI/TIM0_Z/CMP5_IP1/WAKE1/EXTI33P0_4/HALL1_IN1/MCPWM1_BKIN0/UART0_RXD/SPI0_DO/SDA0/TIM0_CH0/TIM3_Z/ADC_TRIGGER1/CAN_TMR/ADC2_CH13/CMP5_IP2/WAKE2/EXTI4/5VT4P0_5/CMP5_OUT/HALL1_IN0/MCPWM0_BKIN3/UART0_TXD/SPI0_CLK/SCL0/TIM0_CH1/TIM2_Z/ADC_TRIGGER0/ADC2_CH12/CMP5_IP3/WAKE3/EXTI5/5VT5P0_6/RST_n/5VT6P0_7/OSC_OUT7P0_8/TIM1_Z/EFLS_DAT[0]/OSC_IN8P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIOTMS/5VT9P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VT10P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLKTCLK/5VT11P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/CAN_TX/CMP4_IP2/WAKE4/EXTI6/TDO/5VT12P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI713P1_1/MCPWM0_CH0N/SPI1_CLK14P1_2/MCPWM0_CH0P/SPI0_CSN15P1_3/MCPWM0_CH1N/SPI0_CLK/SDA1/TIM3_CH016P1_4/MCPWM0_CH1P/SCL1/TIM3_CH0/CAN_TMR/5VT17P1_5/MCPWM0_CH2N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/TIM3_Z/CAN_TX/EXTI9/5VT18P1_6/MCPWM0_CH2P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_RX/5VT19VSS20P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI1121P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_TX/5VT22P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_RX/5VT23P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI1124P1_12/MCPWM1_CH3N/UART2_RXD/SPI0_DI/SCL0/TIM1_CH0/OPA5_IP/EXTI1225P1_13/MCPWM1_CH3P/SPI0_CLK/TIM1_CH1/ADC_TRIGGER0/OPA4_IN26P1_14/MCPWM1_CH2N/SPI0_CSN/TIM1_Z/TIM2_CH0/OPA4_IP27P2_3/MCPWM1_CH2P/TIM1_CH1/CAN_TX/EFLS_DAT[3]28P2_4/MCPWM1_CH1P/TIM2_CH0/CAN_RX/EFLS_CSN29P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/TIM2_CH1/CAN_TMR/EFLS_CLK30P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH131P2_7/MCPWM1_CH1N/SDA0/TIM2_CH0/EXTI1632P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VT64P4_13/CMP0_OUT/HALL0_IN2/SPI1_CLK/SCL0/TIM1_Z/TIM2_Z/CAN_TX/EFLS_DAT[0]/ADC0_CH10/CMP0_IP163VSS3362AVDD61P4_12/CMP1_OUT/HALL1_IN2/UART0_RXD/TIM3_CH0/EFLS_CLK/ADC0_CH12/CMP1_IP360P4_11/HALL1_IN1/TIM3_Z/CMP1_IP259P4_10/HALL1_IN0/TIM3_CH0/CMP1_IP158P4_9/CMP1_OUT/TIM3_CH1/CMP1_IP0/5VT57P4_7/ADC1_CH7/DAC1_OUT56P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO1255P4_5/MCPWM0_CH1P/ADC0_CH11/CMP0_IP0/5VT54P4_0/TIM0_Z/EFLS_DAT[0]/OPA0_IP/EXTI2953P3_15/TIM0_CH0/OPA0_IN/EXTI2852P3_14/OPA1_IP/ADC2_CH4/EXTI2751P3_13/OPA1_IN/ADC2_CH5/EXTI2650P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI2449P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH848P3_9/MCPWM0_BKIN0/TIM0_CH1/OPA2_IN/ADC2_CH947P3_8/MCPWM1_BKIN1/TIM4_CH0/ADC_TRIGGER0/EFLS_CLK/OPA3_IP/ADC2_CH10/EXTI2346P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/EXTI2245P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VT44P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VT43P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/EFLS_DAT[1]/ADC1_CH13/CMP2_IP0/EXTI2142P3_0/HALL1_IN2/MCPWM0_CH2N/TIM3_Z/ADC0_CH14/CMP3_IP1/5VT41P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/EFLS_CLK/CMP3_IP0/EXTI19/5VT40P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/ADC_TRIGGER0/CMP3_IN/WAKE639P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/ADC_TRIGGER1/EFLS_CSN38P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/TIM3_Z/EFLS_DAT[3]/EXTI18/5VT37P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/EFLS_DAT[2]/5VT36P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1]35P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/TIM2_Z/EFLS_DAT[0]34P2_8/MCPWM1_CH0N/SCL0/TIM2_CH1/EXTI1733
Footprint
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
3D Model
Pin Map
PinNameTypeMountShapeWidth × Height (mm)
P0_1/MCPWM1_BKIN2/UART0_RXD/SPI0_CSN/TIM4_CH1/CAN_TX/EXTI1/5VTinputSMDoval0.3×1.5
P0_2/CMP5_OUT/MCPWM1_BKIN3/UART0_TXD/CAN_RX/CMP5_IP0/WAKE0/EXTI2/5VToutputSMDoval0.3×1.5
P0_3/HALL1_IN2/SPI0_DI/TIM0_Z/CMP5_IP1/WAKE1/EXTI3ioSMDoval0.3×1.5
P0_4/HALL1_IN1/MCPWM1_BKIN0/UART0_RXD/SPI0_DO/SDA0/TIM0_CH0/TIM3_Z/ADC_TRIGGER1/CAN_TMR/ADC2_CH13/CMP5_IP2/WAKE2/EXTI4/5VTpassiveSMDoval0.3×1.5
P0_5/CMP5_OUT/HALL1_IN0/MCPWM0_BKIN3/UART0_TXD/SPI0_CLK/SCL0/TIM0_CH1/TIM2_Z/ADC_TRIGGER0/ADC2_CH12/CMP5_IP3/WAKE3/EXTI5/5VTpassiveSMDoval0.3×1.5
P0_6/RST_n/5VTpassiveSMDoval0.3×1.5
P0_7/OSC_OUTpassiveSMDoval0.3×1.5
P0_8/TIM1_Z/EFLS_DAT[0]/OSC_INpassiveSMDoval0.3×1.5
P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIOTMS/5VTpassiveSMDoval0.3×1.5
P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VTpassiveSMDoval0.3×1.5
P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLKTCLK/5VTpassiveSMDoval0.3×1.5
P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/CAN_TX/CMP4_IP2/WAKE4/EXTI6/TDO/5VTpassiveSMDoval0.3×1.5
P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI7passiveSMDoval0.3×1.5
P1_1/MCPWM0_CH0N/SPI1_CLKpassiveSMDoval0.3×1.5
P1_2/MCPWM0_CH0P/SPI0_CSNpassiveSMDoval0.3×1.5
P1_3/MCPWM0_CH1N/SPI0_CLK/SDA1/TIM3_CH0passiveSMDoval0.3×1.5
P1_4/MCPWM0_CH1P/SCL1/TIM3_CH0/CAN_TMR/5VTpassiveSMDoval1.5×0.3
P1_5/MCPWM0_CH2N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/TIM3_Z/CAN_TX/EXTI9/5VTpassiveSMDoval1.5×0.3
P1_6/MCPWM0_CH2P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_RX/5VTpassiveSMDoval1.5×0.3
VSSgroundSMDoval1.5×0.3
P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI11passiveSMDoval1.5×0.3
P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_TX/5VTpassiveSMDoval1.5×0.3
P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_RX/5VTpassiveSMDoval1.5×0.3
P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI11passiveSMDoval1.5×0.3
P1_12/MCPWM1_CH3N/UART2_RXD/SPI0_DI/SCL0/TIM1_CH0/OPA5_IP/EXTI12passiveSMDoval1.5×0.3
P1_13/MCPWM1_CH3P/SPI0_CLK/TIM1_CH1/ADC_TRIGGER0/OPA4_INpassiveSMDoval1.5×0.3
P1_14/MCPWM1_CH2N/SPI0_CSN/TIM1_Z/TIM2_CH0/OPA4_IPpassiveSMDoval1.5×0.3
P2_3/MCPWM1_CH2P/TIM1_CH1/CAN_TX/EFLS_DAT[3]passiveSMDoval1.5×0.3
P2_4/MCPWM1_CH1P/TIM2_CH0/CAN_RX/EFLS_CSNpassiveSMDoval1.5×0.3
P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/TIM2_CH1/CAN_TMR/EFLS_CLKpassiveSMDoval1.5×0.3
P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH1passiveSMDoval1.5×0.3
P2_7/MCPWM1_CH1N/SDA0/TIM2_CH0/EXTI16passiveSMDoval1.5×0.3
P2_8/MCPWM1_CH0N/SCL0/TIM2_CH1/EXTI17passiveSMDoval0.3×1.5
P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/TIM2_Z/EFLS_DAT[0]passiveSMDoval0.3×1.5
P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1]passiveSMDoval0.3×1.5
P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/EFLS_DAT[2]/5VTpassiveSMDoval0.3×1.5
P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/TIM3_Z/EFLS_DAT[3]/EXTI18/5VTpassiveSMDoval0.3×1.5
P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/ADC_TRIGGER1/EFLS_CSNpassiveSMDoval0.3×1.5
P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/ADC_TRIGGER0/CMP3_IN/WAKE6passiveSMDoval0.3×1.5
P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/EFLS_CLK/CMP3_IP0/EXTI19/5VTpassiveSMDoval0.3×1.5
P3_0/HALL1_IN2/MCPWM0_CH2N/TIM3_Z/ADC0_CH14/CMP3_IP1/5VTpassiveSMDoval0.3×1.5
P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/EFLS_DAT[1]/ADC1_CH13/CMP2_IP0/EXTI21passiveSMDoval0.3×1.5
P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VTpassiveSMDoval0.3×1.5
P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VTpassiveSMDoval0.3×1.5
P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/EXTI22passiveSMDoval0.3×1.5
P3_8/MCPWM1_BKIN1/TIM4_CH0/ADC_TRIGGER0/EFLS_CLK/OPA3_IP/ADC2_CH10/EXTI23passiveSMDoval0.3×1.5
P3_9/MCPWM0_BKIN0/TIM0_CH1/OPA2_IN/ADC2_CH9passiveSMDoval0.3×1.5
P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH8passiveSMDoval0.3×1.5
P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI24passiveSMDoval1.5×0.3
P3_13/OPA1_IN/ADC2_CH5/EXTI26passiveSMDoval1.5×0.3
P3_14/OPA1_IP/ADC2_CH4/EXTI27passiveSMDoval1.5×0.3
P3_15/TIM0_CH0/OPA0_IN/EXTI28passiveSMDoval1.5×0.3
P4_0/TIM0_Z/EFLS_DAT[0]/OPA0_IP/EXTI29passiveSMDoval1.5×0.3
P4_5/MCPWM0_CH1P/ADC0_CH11/CMP0_IP0/5VTpassiveSMDoval1.5×0.3
P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO12passiveSMDoval1.5×0.3
P4_7/ADC1_CH7/DAC1_OUTpassiveSMDoval1.5×0.3
P4_9/CMP1_OUT/TIM3_CH1/CMP1_IP0/5VTpassiveSMDoval1.5×0.3
P4_10/HALL1_IN0/TIM3_CH0/CMP1_IP1passiveSMDoval1.5×0.3
P4_11/HALL1_IN1/TIM3_Z/CMP1_IP2passiveSMDoval1.5×0.3
P4_12/CMP1_OUT/HALL1_IN2/UART0_RXD/TIM3_CH0/EFLS_CLK/ADC0_CH12/CMP1_IP3passiveSMDoval1.5×0.3
AVDDpowerSMDoval1.5×0.3
VSS33passiveSMDoval1.5×0.3
P4_13/CMP0_OUT/HALL0_IN2/SPI1_CLK/SCL0/TIM1_Z/TIM2_Z/CAN_TX/EFLS_DAT[0]/ADC0_CH10/CMP0_IP1passiveSMDoval1.5×0.3
P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VTpassiveSMDoval1.5×0.3

Key Parameters

Frequency
192MHz

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Details

Category
microcontroller
MPN
LKS32MC453RCT8
Manufacturer
LINKOSEMI
Package
LQFP-64(10x10)
Footprint
LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL
JLCPCB
C5204706
LCSC
C5204706
Lifecycle
active
Mounting
SMT
RoHS
Compliant
MSL
MSL 3
ECCN
-

JLCPCB Stock & Pricing

In Stock(1,325 pcs)
1-9 pcs$2.1703
10-29 pcs$1.8426
30-159 pcs$1.6370
160-479 pcs$1.4265
480-959 pcs$1.3318
960+ pcs$1.2900